1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly an input protective circuit arranged between an input/output terminal and an internal circuit of a semiconductor integrated circuit or the like and a method of manufacturing the same.
2. Description of the Related Art
In some cases, an excess surge voltage higher than the breakdown voltage of the internal circuit is applied to the input/output terminal of a semiconductor integrated circuit or the like by, e.g., static electricity. If this excess surge voltage is directly applied to the internal circuit, the internal circuit is destroyed. A normal semiconductor integrated circuit has an input protective circuit between the input/output terminal and the internal circuit. With this structure, even when an excess surge voltage is applied to the input/output terminal, application of the surge voltage to the internal circuit can be prevented.
In this input protective circuit, a resistance element is connected to a bonding pad serving as an input/output terminal to which a wire is bonded, and the internal circuit is connected to this resistance element through the wiring layer. The wiring layer is also connected to the drain diffusion layer of an n-channel transistor, and a grounding supply is connected to the source diffusion layer and gate electrode of the transistor through the wiring layer. The input protective circuit is constituted by the resistance element and the transistor.
The transistor of this input protective circuit is not turned on even when a voltage with a predetermined value or less is applied to the bonding pad. Therefore, the current flows from the bonding pad to the internal circuit through the resistance element and the wiring layer.
However, when a voltage with a value larger than the predetermined value is applied to the bonding pad, the peak voltage is lowered by .tau.=C.times.R, which is determined by a parasitic capacitance C in the wiring layer and a resistance value R of the resistance element. At the same time, the current flows to the grounding supply through the transistor in which snapback breakdown occurs, thereby lowering the voltage applied to the internal circuit.
In the conventional input protective circuit, however, since an element active region where a pair of n.sup.+ -type diffusion layers serving as the drain and source of the transistor are formed, and an element active region where an n.sup.- -type diffusion layer serving as the resistance element is formed, are separated from each other by a field oxide film as an element isolation structure, a large area is necessary for the input protective circuit due to the area of the field oxide film. Consequently, the semiconductor integrated circuit or the like can hardly be micropatterned.
A structure in which diffusion layers are not separated by a field oxide film is disclosed in, e.g., Japanese Patent Laid-Open No. 57-90969. In Japanese Patent Laid-Open No. 57-90969, a diode is used for the input protective circuit, and a p.sup.- -type diffusion layer and a p.sup.+ -type diffusion layer are formed to overlap each other, thereby raising the electrostatic breakdown voltage. However, since the p.sup.- -type diffusion layer and the p.sup.+ -type diffusion layer are stacked, this structure cannot be used as a resistance element.